View Issue Details
| ID | Project | Category | View Status | Date Submitted | Last Update |
|---|---|---|---|---|---|
| 0000541 | T99X171.00 SKB Eagle | HW | public | 2019-03-08 11:31 | 2019-04-29 16:38 |
| Reporter | Assigned To | (HW) Sean Chiang | Due Date | 2019-03-08 11:00 | |
| Priority | immediate | Severity | s1-catastrophic | Reproducibility | have not tried |
| Status | closed | Resolution | fixed | ||
| Summary | 0000541: [DDR, EMMC] aging test | ||||
| Description | Hi Sean. I commen that DDR and eMMC Aging test can be replaced to power on/off test of reliability test but It is too late DDR and EMMC aging test at reliability test. for quick varification, Do DDR and eMMC aging test at only board state (without tool) Please let me know the test schedule. | ||||
| Tags | No tags attached. | ||||
| Attach Tags | |||||
| User List |
(ALTech) BY Lee , |
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OK, will get back to you the schedule early of next week. |
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Hi SB, As per mentioned in the weekly meeting, we are lack of PCBA now. There is only one PCBA in our Hsinchu office and we use that PCBA to verify the Ethernet 10M and USB3.0 RX So, once we finish the SI test, we will arrange Aging test in our HWQA Lab. In addition, we have worked with Amlogic to verify below two test items to ensure that the DDR and eMMC is stable during the EVT build 1. Run a DDR read/write test script about 20mins with 10pcs PCBAs. We will log all the message and provide to Amlogic to verify & fine tune theDDR timing window. For Eagle board, Amlogic have done one time fine tune and has approved our DDR timing in 2nd time log file(ddr_test_log_0220). I attached two times log file for your reference (1st time test log: ddr_test_log, 2nd time test log: ddr_test_log_0220). 2. Do 72hrs burning test with 3pcs PCBAs (Each PCBA will be put in a sealing box seperately) @ 25deg. ambient temperature. The PCBA will running with a test program which provied by Amlogic for full loading test. |
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Attached DDR timing log file. |
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HI Sean I saw the file ddr_test. that is just log message file. please make the report using this log message. include setup diagram, result (pass/fail) |
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Hi Sean please update the report of DDR/EMMC aging replacemet test |
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Hi SB, Because we didn't record the test environment/ result for the DDR read/write test in the beginning of EVT build, it's hard to make the complete report for now. So, I am arranging the Aging test in our HWQA team now. We will try to finish Aging test by this week. Will update you the result soon. |
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I received the anging and power onoff test report. I close this issue. if other issue appears, I'll manage to ID :0000543. |
| Date Modified | Username | Field | Change |
|---|---|---|---|
| 2019-03-08 11:31 |
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New Issue | |
| 2019-03-08 11:31 |
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Status | new => assigned |
| 2019-03-08 11:31 |
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Assigned To | => (HW) Sean Chiang |
| 2019-03-08 11:32 |
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Issue Monitored: (ALTech) SY Yoon | |
| 2019-03-08 11:32 |
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Issue Monitored: (ALTech) Philip | |
| 2019-03-08 11:32 |
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Issue Monitored: (PM) Sheila Tu | |
| 2019-03-08 11:32 |
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Issue Monitored: (ALTech) Eric Kim | |
| 2019-03-08 11:32 |
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Issue Monitored: (ALTech) Jewoo Lee | |
| 2019-03-08 20:38 | (HW) Sean Chiang | Note Added: 0001426 | |
| 2019-03-29 21:22 | (HW) Sean Chiang | Note Added: 0001780 | |
| 2019-03-29 21:23 | (HW) Sean Chiang | File Added: ddr_test_log.zip | |
| 2019-03-29 21:23 | (HW) Sean Chiang | File Added: ddr_test_log_0220.zip | |
| 2019-03-29 21:23 | (HW) Sean Chiang | Note Added: 0001781 | |
| 2019-04-01 17:16 |
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Note Added: 0001800 | |
| 2019-04-09 22:09 |
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Note Added: 0001932 | |
| 2019-04-10 00:20 | (HW) Sean Chiang | Note Added: 0001938 | |
| 2019-04-29 16:37 |
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Issue Monitored: (ALTech) Juyoung Park | |
| 2019-04-29 16:37 |
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Issue Monitored: (ALTech) BY Lee | |
| 2019-04-29 16:38 |
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Status | assigned => closed |
| 2019-04-29 16:38 |
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Resolution | open => fixed |
| 2019-04-29 16:38 |
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Note Added: 0002279 |
